Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices conventionally use a one-transistor memory device that provides high memory densities, high reliability, and low power consumption. NAND is a major form of Flash memory that was designed with a small device size to provide low cost-per-bit data storage and has been primarily used as a high-density storage medium for consumer devices. Common uses for NAND are consumer devices, such as portable audio/video storage devices, personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones.
A conventional NAND device comprises a memory array including rows and columns of memory cells. Each of the memory cells conventionally includes a field-effect transistor having a control gate and a floating gate. The floating gate is capable of holding a charge and is separated by a thin oxide layer from source, drain, and channel regions contained in a substrate. Each of the memory cells can be electrically programmed (charged) by injecting electrons from the channel region through the oxide layer onto the floating gate. The charge can be removed from the floating gate by tunneling the electrons to the channel region through the oxide layer during an erase operation. Thus, the data in a memory cell is determined by the presence or absence of a charge on the floating gate.
Conventional NAND memory devices include an array of memory cells coupled to form a linear sequence of cells, often referred to as a “string,” such that each memory cell is coupled indirectly to a bit line and requires activating the other devices of the string for access. Conventionally, the control gate of each memory cell of a row of the array is connected to a conductive line (e.g., a wordline) having a common voltage, and the drain region of each memory cell of a column of the array is connected to another conductive line (e.g., a bit line) having a common voltage.
As the performance and complexity of electronic systems increase, the requirement for additional memory in memory systems also increases. Moreover, to reduce costs of fabricating such memory arrays, the parts count must be kept to a minimum. This means being able to achieve a higher density of memory on a single chip instead of by stacking separate memory chips. This is often done by reducing the feature size of the memory cell. However, feature sizes of the devices are often limited by device characteristics before a desired, reduced feature size may be reached. In NAND memory arrays in particular, as the channel length and width are reduced and the spacing between memory cells in the arrays are reduced, a minimum feature size may be dictated by the operational characteristics of the memory cells that make up the memory arrays.